How to Design Layout with RP2350

Earlier as an electronics engineer I have designed a lot of 2-4 layers development boards, some are clones, some with better functionality. The designing of development boards unlocks the design potentials of a PCB designer, moreover we can learn a lot of new things, routing procedures through this hardware ground research. The design of our own development board is related to customization, with some little effort we can tune the PCB according to our requirements. Sometimes in order to reduce the overall cost of a system the minimal system for a microcontroller is prepared and used as a shield.

The Minimal Board Overview:

The original Minimal board was an attempt to provide a simple reference design, using the bare minimum of external components required to run the RP2350 while keeping all the I/O exposed and accessible. It consisted of:

• A power source (5V to 3.3V linear regulator)
• A crystal oscillator
• Flash memory
• I/O connections (micro USB socket and GPIO headers)

The new RP235x series Minimal boards retain much of the same design but with necessary modifications to accommodate the new hardware. Additionally, despite the minimalistic approach, BOOTSEL and RUN buttons, along with a separate SWD header, have been included to improve the debugging experience. While these buttons are not strictly necessary since the signals remain accessible on headers they can be omitted if cost or space constraints are a priority. Now it’s our time to make a custom PCB with RP2350 functionality on it.

RP2040 vs RP235x Series:

The Raspberry Pi RP2350 represents a major evolution in microcontroller design, featuring:

• Dual-core ARM Cortex-M33 processors
• Dual RISC-V cores
• 150 MHz clock speed
• 520 KB SRAM
• Hardware security accelerators.

RP2350 has two different series A and B, the difference between the two are listed below:

Design Flow and Requirements:

The Minimal board design aims to create manufacturable, cost-effective solutions using the RP235x series without requiring advanced PCB technologies. Key design choices include:

• 2-layer PCB
• Commonly available components
• All components mounted on the top layer

While larger, hand-solderable components would be preferable, the 0.4mm pitch of the QFN chips necessitates the use of 0402 (1005 metric) passives to fully utilize all GPIOs. Although 0402 components can be soldered manually with the right tools, QFNs require specialized equipment. The design includes two separate PCBs, one for each package size. Component references (e.g., U1, R1) are consistent across both designs, except where unique elements exist (e.g., R13 on QFN-80 design only).

Schematic and Layout Sections of RP2350:

The design flow include:

1. Power Section
2. Decoupling capacitor section
3. Flash memory section
4. PSRAM section
5. Crystal oscillator section
6. I/O section
7. Buttons

Power Section:

First the input USB 5V is converted to 3.3 volts, which serves as input voltage to RP2350. The conversion is done with the help of a linear voltage regulator.

In the layout section keep the 10u input and output capacitors near to NCP1117 voltage regulator to keep the power supply noise free. The linear regulator of the RP2040 had two pins, a 3.3V input, and a 1.1V output to supply the DVDD on the chip. This time, the regulator of the RP235x series has five pins, and requires some external componentry to make it work.

The directionality of these small inductors is pretty much universally ignored, with the orientation of the coil winding impossible to deduce, and also randomly distributed along a reel of components. Larger inductor case sizes can often be found to have polarity markings on them, however we could find no suitable ones in the 0806 (2016 metric) case size. For that a special Abracon 3.3μH inductor with a dot to indicate polarity is used in the circuit. The AOTA-B201610S3R3-101-T are (or will very shortly) be made available to the general public from distributors.

As mentioned earlier, the VREG_AVDD supply is very sensitive to noise,  and therefore needs to be filtered. We found that as the VREG_AVDD only draws around 200μA, an RC filter of 33Ω and 4.7μF is adequate. A pretty good example of layout can be seen below, how closely the section is made with respect to the position of the IC.

Decoupling Capacitor Section:

Another aspect of the power supply design are the decoupling capacitors required for RP2350. These provide two basic functions. Firstly, they filter out power supply noise, and secondly, provide a local supply of charge that the circuits inside RP2350 can use at short notice. This prevents the voltage level in the immediate vicinity from dropping too much when the current demand suddenly increases. Place 100nF ceramic capacitors within 2mm of each VDD pin, supplemented by 10µF bulk capacitors per power domain.

Because of this, it is important to place decoupling close to the power pins. Ordinarily, we recommend the use of a 100nF capacitor per power pin, however, we deviate from this rule in a couple of instances. See the example layout here:

Flash Memory/PSRAM Section:

RP2350 has no internal flash. Of course, the RP2354 devices have internal 2MB flash memories, so the external U3 memory is not required, so U3 can safely be removed from the schematic, or simply left unpopulated. QSPI Routing: Matched length traces (ΔL < 150µm) with 50Ω impedance control.

Configuration as Primary Memory:

In order to be able to store program code which RP2350 can boot and run from, we need to use a flash memory, specifically, a quad SPI flash memory. The device chosen here is an W25Q128JVS device, which is a 128Mbit chip (16MB). This is the largest memory size that RP2350 can support. If your particular application doesn’t need as much storage, then smaller, cheaper memory options are also there.

As this databus can be quite high frequency and is regularly in use, the QSPI pins of RP2350 should be wired directly to the flash, using short connections to maintain the signal integrity, and to also reduce crosstalk in surrounding circuits. Crosstalk is where signals on one circuit net can induce unwanted voltages on a neighbouring circuit, potentially causing errors to occur.

Although to make connections properly some resistors a total of 4 are used, The first (R1) is a pull-up to the 3.3V supply. The flash memory requires the chip select input to be at the same voltage as its own 3.3V supply pin as the device is powered up, otherwise, it does not function correctly. The second resistor (R6) is a 1kΩ resistor, connected to a push button (SW1) labelled 'USB_BOOT'. This is because the QSPI_SS pin is used as a 'boot strap'; RP2350 checks the value of this I/O during the boot sequence, and if it is found to be a logic 0, then RP2350 reverts to the BOOTSEL mode, where RP2350 presents itself as a USB mass storage device, and code can be copied directly to it.  

Configuration as Secondary Memory:

So, if we are using an RP2354 (which has an internal flash), then we could use U3 as a secondary flash, or even replace it with a PSRAM device. In order to do this, we need to disconnect QSPI_SS from U3, and connect it to a suitable GPIO instead. The nearest GPIO capable of being a chip select (XIP_CS1n) is GPIO0, so by removing the 0Ω from R10, and fitting it to R9, we can now access U3 in addition to the on-chip flash. In order to fully take advantage of this feature, where we have two external memory devices so that the flash-less RP2350 parts can benefit, the larger of the two Minimal boards, for the RP2350B, includes an optional footprint (U4) for an additional memory chip.

To be able to use this device, it will obviously have to be populated , as well as R11 (0Ω), and R13 (10KΩ). The addition of R11 connects GPIO0 (the XIP_CS1n signal) to the chip select of the second memory. The pull-up on the chip select pin is definitely needed this time, as the default state of GPIO0 is to be pulled low at power-up, which would cause our flash device to fail. C22 would also be needed to provide local power supply decoupling for U4. These resistors (R9 and R10 also), should be placed close to the flash chip, so we avoid additional lengths of copper tracks which could affect the signal.

I/O Section:

In addition to the USB connector already mentioned, there are a pair of dual row 2.54mm headers, one on each side of the board, to which the rest of the I/O have been connected. There are 30 GPIO on the RP2350A, whereas there are 48 GPIO on the RP2350B, so the headers on this version of the Minimal board are larger to allow for the extra pins. The inner row of pins on each header are the I/Os, and the outer row are all connected to ground. It is good practice to include many grounds on I/O connectors. This helps to maintain a low impedance ground, and also to provide plenty of potential return paths for currents travelling to and from the I/O connections.

Both headers are on the same 2.54mm grid, which makes connecting this board to other things, such as breadboards, easier. You might want to consider fitting only a single row header instead of the dual row header, dispensing with the outer row of ground connections, to make it more convenient to fit to a breadboard.

Buttons:

The RP2350 is based on the RP2040 microcontroller, so if you're referring to a development board with the RP2350, the onboard buttons typically include:

1. BOOTSEL Button – Used to enter boot mode for flashing firmware via USB.
2. RESET Button – Used to reset the microcontroller.

These buttons are common on Raspberry Pi RP2040-based boards, including the Raspberry Pi Pico. Some custom RP2350 development boards may also include additional user-programmable buttons. The configuration and circuit diagram can be found in the main schematics shared at the end of this document.

Crystal Oscillator Section:

Strictly speaking, RP2350 does not actually require an external clock source, as it has its own internal oscillator. However, as the frequency of this internal oscillator is not well defined or controlled, varying from chip to chip, as well as with different supply voltages and temperatures, it is recommended to use a stable external frequency source. Applications which rely on exact frequencies are not possible without an external frequency source, USB being a prime example.

Providing an external frequency source can be done in one of two ways: either by providing a clock source with a CMOS output (square wave of IOVDD voltage) into the XIN pin, or by using a 12MHz crystal connected between XIN and XOUT.

Using a crystal is the preferred option here, as they are both relatively cheap and very accurate. The chosen crystal for this design is an ABM8-272-T3 (Y1 in Figure 10). This is the same 12MHz crystal used on the Raspberry Pi Pico and Raspberry Pi Pico 2. We highly recommend using this crystal along with the accompanying circuitry to ensure that the clock starts quickly under all conditions without damaging the crystal itself. The crystal has a 30ppm frequency tolerance, which should be good enough for most applications. Along with a frequency tolerance of +/-30ppm, it has a maximum ESR of 50Ω, and a load capacitance of 10pF, both of which had a bearing on the choice of accompanying components. For a crystal to oscillate at the desired frequency, the manufacturer specifies the load capacitance that it needs for it to do so, and in this case, it is 10pF. This load capacitance is achieved by placing two capacitors of equal value, one on each side of the crystal to ground (C3 and C4). From the crystal’s point of view, these capacitors are connected in series between its two terminals.

For original RP2350 designs, we recommend using the Abracon ABM8-272-T3 crystal. This component is utilized in the minimal design example, as well as in the Pico 2 board schematic found in Appendix B of the Raspberry Pi Pico 2 Datasheet and the Pico 2 design files.

For optimal performance and stability across standard operating temperature ranges, the ABM8-272-T3 is the preferred choice. It can be sourced directly from Abracon or through an authorized reseller. The Pico 2 board has been specifically tuned for this crystal, which features the following specifications:

• Model: Abracon ABM8-272-T3
• Operating Voltage: 3.3V (tuned for IOVDD voltage)
• Frequency Stability: Optimized for temperature variations

If you decide to use a crystal with similar specifications, thorough testing across various temperatures is essential to ensure circuit stability. Since the crystal oscillator is powered by the IOVDD voltage, the Abracon crystal and corresponding damping resistor are tuned for 3.3V operation. If you opt for a different IO voltage, re-tuning will be necessary. Any modifications to the crystal parameters could introduce instability in components connected to the oscillator circuit.

Fabricating at JLCPCB:

Open Source Projects on RP2350:

Schematics RP2350:

Project on RP2350: See through this link

Project on RP2040: See through this link